Low Power Two-Tier GALS Architecture for Multi Robot Collision Avoidance

Neeraj Pradhan    Roopak Dubey    K. Madhava Krishna    Shubhajit Roy Chowdhury   

IIIT Hyderabad, India   

This paper presents a Field Programmable Gate Array (FPGA) based implementation of Acceleration Velocity Obstacle based Collision Avoidance for an omni-directional robot with acceleration constraint. A novel Globally Asynchronous-Locally Synchronous (GALS) architecture using hybrid parallel-pipelined design is being used for the implementation. FPGA offers highly parallel hardware architectures that are not possible on conventional high end processors or other embedded controllers. Specifically, a parallel architecture for collision avoidance is proposed that portrays the advantages of FPGA implementation over the sequential implementation for same processor or clock speed with the objective of parallelizing the computation. The proposed two-tier GALS architecture based system with hybrid parallel-pipelined architectural design when realized on FPGA shows its efficiency in terms of power, resources and response time in comparison with a conventional GALS design. Due to the asynchronous design, a good amount of logic in the hardware becomes combinational logic and hence a significant reduction in the total resource utilization and power-delay product (PDP) in the proposed architecture is observed. This paper also shows the clear advantage of using the FPGA instead of a general purpose processor for robotic system design.