FPGA based Hierarchical Architecture for Parallelizing RRT

Gurshaant Singh Malik    Krishna Gupta    Shubhajit Roy    Chowdhury    K. Madhava Krishna   

IIIT Hyderabad, India   

This paper presents a new hierarchical architecture for parallelizing the computation intensive rapidly exploring random tree problem. The architecture resembles a tree like structure that agglutinates minimal inter-module communication of a shared memory with data integrity of a distributed memory. Another novelty of this research has been in quantitatively analysing the performance metrics of the RRT algorithm across numerous embedded hardware solutions and ultimately implementing this algorithm on an FPGA to achieve hardware level optimization that offers real time performance and economical power consumption levels. We then analyse our implementation against hardware implementation of other scalable parallel RRT methods for motion planning